15 research outputs found

    Data management of nanometre­ scale CMOS device simulations

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    In this paper we discuss the problems arising in managing and curating the data generated by simulations of nanometre scale CMOS (Complementary Metal–Oxide Semiconductor) transistors, circuits and systems and describe the software and operational techniques we have adopted to address them. Such simulations pose a number of challenges including, inter alia, multi­TByte data volumes, complex datasets with complex inter-relations between datasets, multi­-institutional collaborations including multiple specialisms and a mixture of academic and industrial partners, and demanding security requirements driven by commercial imperatives. This work was undertaken as part of the NanoCMOS project. However, the problems, solutions and experience seem likely to be of wider relevance, both within the CMOS design community and more generally in other disciplines

    Secure, performance-oriented data management for nanoCMOS electronics

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    The EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is focused upon delivering a production level e-Infrastructure to meet the challenges facing the semiconductor industry in dealing with the next generation of ‘atomic-scale’ transistor devices. This scale means that previous assumptions on the uniformity of transistor devices in electronics circuit and systems design are no longer valid, and the industry as a whole must deal with variability throughout the design process. Infrastructures to tackle this problem must provide seamless access to very large HPC resources for computationally expensive simulation of statistic ensembles of microscopically varying physical devices, and manage the many hundreds of thousands of files and meta-data associated with these simulations. A key challenge in undertaking this is in protecting the intellectual property associated with the data, simulations and design process as a whole. In this paper we present the nanoCMOS infrastructure and outline an evaluation undertaken on the Storage Resource Broker (SRB) and the Andrew File System (AFS) considering in particular the extent that they meet the performance and security requirements of the nanoCMOS domain. We also describe how metadata management is supported and linked to simulations and results in a scalable and secure manner

    Integrating security solutions to support nanoCMOS electronics research

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    The UK Engineering and Physical Sciences Research Council (EPSRC) funded Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is developing a research infrastructure for collaborative electronics research across multiple institutions in the UK with especially strong industrial and commercial involvement. Unlike other domains, the electronics industry is driven by the necessity of protecting the intellectual property of the data, designs and software associated with next generation electronics devices and therefore requires fine-grained security. Similarly, the project also demands seamless access to large scale high performance compute resources for atomic scale device simulations and the capability to manage the hundreds of thousands of files and the metadata associated with these simulations. Within this context, the project has explored a wide range of authentication and authorization infrastructures facilitating compute resource access and providing fine-grained security over numerous distributed file stores and files. We conclude that no single security solution meets the needs of the project. This paper describes the experiences of applying X.509-based certificates and public key infrastructures, VOMS, PERMIS, Kerberos and the Internet2 Shibboleth technologies for nanoCMOS security. We outline how we are integrating these solutions to provide a complete end-end security framework meeting the demands of the nanoCMOS electronics domain

    Scalable, security-oriented solutions for nanoCMOS electronics

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    The EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS – www.nanocmos.ac.uk) has been funded to tackle some of the challenges facing the semiconductor electronics industry caused by the progressive scaling of CMOS transistors. As transistor dimensions are now at the nanometer scale with 40nm MOSFETs already in mass production and sub-10 nm transistors scheduled for production by 2018, the intrinsic parameter fluctuations caused by the inherent discreteness of charge and matter at this atomistic scale are now one of the major challenges that the semiconductor electronics industry needs to address. The variability at the device level affects profoundly the circuit/system design process and hence can be regarded a semiconductor industry-wide problem. Fortunately many of the statistical variability related issues can be understood and forecasted through large scale simulation of ensembles of potentially hundreds of thousands of atomistically varying devices. However, one of the main distinguishing features of NanoCMOS when compared to other high performance computing (HPC) simulation domains is the imperative requirements on fine grained security. The data, the designs and even the simulations themselves all potentially have highly sensitive commercial intellectual property (IP) value associated with them, ranging from the IP of device manufacturers and the design houses through to licenses needed to run simulation and design software. This paper outlines the e-Infrastructure that has been developed within the nanoCMOS project with specific focus upon the security capabilities it supports and how these address the IP protection requirements of the industrial and collaborating partners. Our ultimate goal is to provide an environment that addresses security across the board and scales to meet the HPC and data management requirements of nanoCMOS research

    Pulsar virtual observatory

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    The Pulsar Virtual Observatory will provide a means for scientists in all fields to access and analyze the large data sets stored in pulsar surveys without specific knowledge about the data or the processing mechanisms. This is achieved by moving the data and processing tools to a grid resource where the details of the processing are seen by the users as abstract tasks. By developing intelligent scheduling middle-ware the issues of interconnecting tasks and allocating resources are removed from the user domain. This opens up large sets of radio time-series data to a wider audience, enabling greater cross field astronomy, in line with the virtual observatory concept. Implementation of the Pulsar Virtual Observatory is underway, utilising the UK National Grid Service as the principal grid resource.Comment: Proceedings of the 363. WE-Heraeus Seminar on: Neutron Stars and Pulsars (Posters and contributed talks) Physikzentrum Bad Honnef, Germany, May.14-19, 2006, eds. W.Becker, H.H.Huang, MPE Report 291, pp.223-22

    A resource-oriented data management architecture for nanoCMOS electronics

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    The EPSRC pilot project Meeting the Design Challenges of NanoCMOS Electronics (nanoCMOS) began in October 2006 and is focused upon tackling the decreasing scale of modern semiconductor components. This scaling has direct impact upon the complete circuit and system electronics design process due to the variability in transistor behaviour caused by differences in atomic structure. To address these challenges, the project has focused upon large scale device simulations exploiting a wide variety of computational resources. This paper focuses on the approach adopted for managing the many hundreds of thousands of files being generated that are associated with these simulations. Specific challenges in achieving this are related to the fine grained security demanded in protecting intellectual property of data and metadata, and the seamless linkage of metadata associated with services. We believe that this data architecture has widespread applicability to many research areas

    Multi-level simulations to support nanoCMOS electronics research

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